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CYUSB202X sd2? usb and mass storag e peripheral controller cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-87710 rev. *c revised april 24, 2017 features latest-generation storage support ? sd2.0/sdxc ? uhs1 sdr50 / ddr50 master ? emmc 4.4 master ? sdio 3.0 master usb integration ? certified usb 2.0 peripheral: hi-speed (hs), and full-speed (fs) only) ? thirty-two physical endpoints ? integrated transceiver ? accessory charger adaptor (aca) support ultra low-power in core power-down mode ? less than 60 a with vbatt on and 20 a with vbatt off i 2 c master controller at 1 mhz selectable input clock frequencies ? 19.2, 26, 38.4, and 52 mhz ? 19.2-mhz crystal input support independent power domains for core and i/o 10 10 mm, 0.8-mm pitch ball grid array (bga) package applications usb thumb drives card readers laptop with sd slots sd slot in tv/stb wifi dongles logic block diagram usb eps gpios hs/fs peripheral d+ d- usb interface sdio/sd/mmc controller s0-port s1-port i2c i 2 c_scl i 2 c_sda fslc[0] fslc[1] fslc[2] clkin clkin_32 xtalin xtalout s0_sd0 s0_sd1 s0_sd2 s0_sd3 s0_sd4 s0_sd5 s0_sd6 s0_sd7 s0_cmd s0_clk s0_wp s0s1_ins mmc0_rst_out s1_sd0 s1_sd1 s1_sd2 s1_sd3 s1_sd4 s1_sd5 s1_sd6 s1_sd7 s1_cmd s1_clk mmc1_rst_out s1_wp arm926ej-s jtag embedded sram (512 kb/ 256 kb) tdi tdo trst# tms tck uart spi i 2 s
CYUSB202X document number: 001-87710 rev. *c page 2 of 27 contents functional overview ........................................................ 3 usb interface (u-port) ................................................ 3 mass-storage support (s-port) ................................... 3 i2c interface ................................................................ 3 uart interface ............................................................ 3 i2s interface ................................................................ 3 spi interface ................................................................ 4 boot options ................................................................ 4 reset ........................................................................... 4 clocking ....................................................................... 4 32-khz watchdog timer clock i nput ............. .............. 4 power .......................................................................... 5 configuration fuse ...................................................... 8 digital i/os ................................................................... 8 emi .............................................................................. 8 system level esd ...................................................... 8 pinout for bga .................................................................. 8 pin description for bga .................................................. 9 ac timing parameters ......... .......................................... 12 storage port timing .................................................. 12 i2c interface timing .................................................. 15 absolute maximum ratings .......................................... 20 operating conditions ..................................................... 20 dc specifications ........................................................... 20 reset sequence ......... .............. .............. .............. ........... 22 package diagram ............................................................ 23 ordering information ...................................................... 24 ordering code definitions ..... .................................... 24 acronyms ........................................................................ 25 document conventions ................................................. 25 units of measure ....................................................... 25 document history page ................................................. 26 sales, solutions, and legal information ...................... 27 worldwide sales and design s upport ......... .............. 27 products .................................................................... 27 psoc? solutions ...................................................... 27 cypress developer community ................................. 27 technical support ................. .................................... 27
CYUSB202X document number: 001-87710 rev. *c page 3 of 27 functional overview sd2? is a usb 2.0 high speed mass-storage controller providing the latest sd/mmc support. sd2 complies with the sd specification, versi on 3.0, and the mmc sp ecification, version 4.41. sd2 offers the following access paths among usb and mass storage ports: a usb-port (u-port) supporting usb 2.0 peripheral two mass-storage ports (s0-port and s1-port) supporting mass-storage devices. followi ng are the possible configura- tions for the two mass-storage ports: ? sd and mmc ? sd and sd ? mmc and mmc ? sd and sdio ? mmc and sdio ? sdio and sdio combinations of these accesses can happen independently or in an interleaved manner. the sd2 complies with the usb 2.0 specification. usb interface (u-port) sd2 offers the following features: supports usb peripheral functionality compliant with the usb 2.0 specification supports up to 16 in and 16 out endpoints. supports the usb 2.0 streams feature. it also supports usb attached scsi (uas) device cl ass to optimize mass-storage access performance. as a usb peripheral, sd2 supports uas and mass storage class (msc) peripheral classes. when the usb port is not in use, the phy and transceiver may be disabled for power savings. figure 1. usb interface signals mass-storage support (s-port) the sd2 storage interface port supports the following specifications: sd specification, version 3.0 multimedia card-system specification, mmca technical committee, version 4.4 sdio host controller compliant with sdio specification version 3.00 i 2 c interface sd2 has an i 2 c interface compatible with the i 2 c bus specification revision 3. because sd2?s i 2 c interface is capable of operating only as an i 2 c master, it may be used to communicate with other i 2 c slave devices. for example, sd2 may boot from an eeprom connected to the i 2 c interface, as a selectable boot option. sd2?s i 2 c master controller also supports multi-master mode functionality. the power supply for the i 2 c interface is vio5, which is a separate power domain from the ot her serial peripherals. this is to allow the i 2 c interface the flexibility to operate at a different voltage than the other serial interfaces. the i 2 c controller supports bus frequencies of 100 khz, 400 khz, and 1 mhz. when vio5 is 1.2 v, the maximum operating frequency supported is 100 khz. when vio5 is 1.8 v, 2.5 v, or 3.3 v, the operating frequencies supported are 400 khz and 1 mhz. the i 2 c controller supports the clock stretching feature to enable slower devices to exercise flow control. both scl and sda signals of the i 2 c interface require external pull-up resistors. these resistors must be connected to vio5. uart interface the uart interface of sd2 supports full-duplex communication. it includes the signals noted in table 1 . the uart is capable of generat ing a range of baud rates, from 300 bps to 4608 kbps, selectable by the firmware. if flow control is enabled, then sd2?s uart only transmits data when the cts input is asserted. in addition to this, sd2?s uart asserts the rts output signal, when it is ready to receive data. i 2 s interface sd2 has an i 2 s port to support external audio codec devices. sd2 functions as i 2 s master as transmitter only. the i 2 s interface consists of four signals: clock line (i2s_clk), serial data line (i2s_sd), word sele ct line (i2s_ws), and master system clock (i2s_mclk). sd2 c an generate the system clock as an output on i2s_mclk or a ccept an external system clock input on i2s_mclk. the sampling frequencies supported by the i 2 s interface are 32 khz, 44.1 khz, and 48 khz. sd3 vbatt vbus usb interface d- d+ table 1. uart interface signals signal description tx output signal rx input signal cts flow control rts flow control
CYUSB202X document number: 001-87710 rev. *c page 4 of 27 spi interface sd2 supports an spi master interface on the serial peripherals port. the maximum operation frequency is 33 mhz. the spi controller supports four modes of spi communication (see spi timing specification on page 18 for details on the modes) with the start-stop clo ck. this controller is a single-master controller with a si ngle automated ssn control. it supports transaction sizes ranging from 4 bits to 32 bits. boot options sd2 can load boot images from va rious sources, selected by the configuration of the pmode pins. the boot options for the sd2 are as follows: boot from usb boot from i 2 c boot from emmc on s0-port boot from spi reset a reset is initiated by asserting the reset# pin on sd2. the specific reset sequence and timing requirements are detailed in figure 3 on page 15 and table 13 on page 22. all i/os are tristated during a hard reset. clocking sd2 allows either a crystal to be connected between the xtalin and xtalout pins or an external clock to be connected at the clkin pin. the xtalin, xtalou t, clkin, and clkin_32 pins can be left unconnected if not used. crystal frequency supported is 19.2 mhz, while the external clock frequencies supported are 19.2, 26, 38.4, and 52 mhz. sd2 has an on-chip oscillator circuit that uses an external 19.2 mhz (100 ppm) crystal (when the crystal option is used). an appropriate load capacitance is required with a crystal. refer to the specification of the cr ystal used to determine the appro- priate load capacitance. the fslc[2:0] pins must be configured appropriately to select the cr ystal option/clock frequency option. the configuration options are shown in table 3 . clock inputs to sd2 must meet the phase noise and jitter require- ments specified in table 4 . the input clock frequency is independent of the clock/data rate of sd2 core or any of the device interfaces. the internal pll applies the appropriate clock multiply option depending on the input frequency. 32-khz watchdog timer clock input sd2 includes a watchdog timer that can be used to interrupt the core, automatically wake up sd2 in standby mode, and reset the core. the watchdog timer runs off a 32-khz clock, which may optionally be supplied from an external source on a dedicated pin of sd2. the watchdog timer can be disabled by firmware. requirements for the optional 32-khz clock input are listed in ta b l e 4 . table 2. booting options for sd2 pmode[2:0] [1] boot from ff0 s0-port: emmc on failure, usb boot enabled ff1 usb boot fff i 2 c on failure, usb boot is enabled 0ff i 2 c only 0f1 spi on failure, usb boot is enabled note 1. f indicates floating. table 3. crystal/clock frequency selection fslc[2] fslc[1] fslc[0] crystal/clock frequency 0 0 0 19.2-mhz crystal 1 0 0 19.2-mhz input clk 1 0 1 26-mhz input clk 1 1 0 38.4-mhz input clk 1 1 1 52-mhz input clk table 4. input clock specifications for sd2 parameter description specification units min max phase noise 100-hz offset ? ?75 db 1-khz offset ? ?104 db 10-khz offset ? ?120 db 100-khz offset ? ?128 db 1-mhz offset ? ?130 db maximum frequency deviation ?150ppm duty cycle 30 70 % overshoot ? 3 % undershoot ? ?3 % rise time/fall time ? 3 ns table 5. 32-khz clock input requirements parameter min max units duty cycle 40 60 % frequency deviation ? 200 ppm rise time/fall time ? 200 ns
CYUSB202X document number: 001-87710 rev. *c page 5 of 27 power sd2 has the following main groups of power supply domains: io_vddq: this refers to a group of independent supply domains for digital i/os. the voltage level on these supplies are 1.8 v to 3.3 v. sd2 prov ides six independent supply domains for digital i/os listed as follows: ? vio2: s0-port (for sd/mmc ) i/o power supply domain ? vio3: s1-port (for sd/mmc ) i/o power supply domain ? vio1: s2-port (gpio) power supply domain ? vio4: s1-port gpio[53:57]/o power supply domain (these pins support mmc?s high nibble data line - d[7:4] on s1-port) ? vio5: i2c power supply domain (supports 1.2 v to 3.3 v) ? cvddq: clock power supply domain vdd: this is the supply voltage for the logic core. the nominal supply voltage level is 1.2 v. this supplies the core logic circuits. the same supply must also be used for the following: ? avdd : this is the 1.2-v supply fo r the pll, crystal oscillator and other core analog circuits vbatt/vbus: this is the 3.2-v to 6-v battery power supply for the usb i/o and analog circuits. this supply powers the usb transceiver through sd2?s internal voltage regulator. vbatt is internally regulated to 3.3 v. power modes sd2 supports the following power modes: normal mode: this is the full-func tional operating mode. in this mode the internal cpu clock and the internal plls are enabled. normal operating power consumption does not exceed the sum of icc_core max and icc_usb max (see table 8 on page 12 for current consumpt ion specifications). the i/o power supplies (vio2, vio3, vio4, and vio5) may be turned off when the corresponding interface is not in use. s2vddq cannot be turned off at any time if the s2-port is used in the application. sd2 supports four low-power modes (see table 6 on page 5): ? suspend mode with usb 2.0 phy enabled (l1 mode) ? suspend mode with usb 2.0 phy disabled (l2 mode) ? standby mode (l3 mode) ? core power-down mode (l4 mode) table 6. entry and exit methods for low-power modes low power mode characteristics methods of entry methods of exit suspend mode with usb 2.0 phy enabled (l1 mode) the power consumption in this mode does not exceed isb 1 usb 2.0 phy is enabled and is in u3 mode (one of the suspend modes defined by the usb 3.0 specification). this one block alone operates with its internal clock while all other clocks are shut down all i/os maintain their previous state power supply for the wakeup source and core power must be retained. all other power domains can be turned on/off individually the states of t he configuration registers, buffer memory and all internal ram are maintained all transactions must be completed before sd2 enters suspend mode (state of outstanding transactions are not preserved) the firmware resumes operation from where it was suspended (except when woken up by reset# assertion) because the program counter does not reset firmware executing on the core can put sd2 into suspend mode. for example, on usb suspend condition, firmwar e may decide to put sd2 into suspend mode d+ transitioning to low or high d? transitioning to low or high resume condition on ssrx +/- detection of vbus assertion of gpio[17] assertion of reset#
CYUSB202X document number: 001-87710 rev. *c page 6 of 27 suspend mode with usb 2.0 phy disabled (l2 mode) the power consumption in this mode does not exceed isb 2 usb 2.0 phy is disabled and the usb interface is in suspend mode the clocks are shut off. the plls are disabled all i/os maintain their previous state usb interface maintains the previous state power supply for the wakeup source and core power must be retained. all other power domains can be turned on/off individually the states of t he configuration registers, buffer memory, and all internal ram are maintained all transactions must be completed before sd2 enters suspend mode (state of outstanding transactions are not preserved) the firmware resumes operation from where it was suspended (except when woken up by reset# assertion) because the program counter does not reset firmware executing on the core can put sd2 into suspend mode. for example, on usb suspend condition, firmwar e may decide to put sd2 into suspend mode d+ transitioning to low or high d? transitioning to low or high resume condition on ssrx +/- detection of vbus assertion of gpio[17] assertion of reset# table 6. entry and exit methods for low-power modes (continued) low power mode characteristics methods of entry methods of exit
CYUSB202X document number: 001-87710 rev. *c page 7 of 27 standby mode (l3 mode) the power consumption in this mode does not exceed isb3 all configuration register settings and program/data ram contents are preserved. however, data in the buffers or other parts of the data path, if any, is not guaranteed. therefore, the external processor should take care that needed data is read before putting sd2 into this standby mode the program counter is reset after waking up from standby gpio pins maintain their configuration crystal oscillator is turned off internal pll is turned off usb transceiver is turned off core is powered down. upon wakeup, the core re-starts and runs the program stored in the program/data ram power supply for the wakeup source and core power must be retained. all other power domains can be turned on/off individually firmware executing on the core or external processor configures the appropriate register detection of vbus assertion of gpio[17] assertion of reset# core power down mode (l4 mode) the power consumption in this mode does not exceed isb 4 core power is turned off all buffer memory, configuration registers and the program ram do not maintain state. it is necessary to reload the firmware on exiting from this mode in this mode, all other power domains can be turned on/off individually turn off vdd reapply vdd assertion of reset# table 6. entry and exit methods for low-power modes (continued) low power mode characteristics methods of entry methods of exit
CYUSB202X document number: 001-87710 rev. *c page 8 of 27 configuration fuse fuse options are available for specific usage models. contact cypress applications/marketing for details. digital i/os sd2 provides firmware controlled pull-up or pull-down resistors internally on all digital i/o pins. the pins can be pulled high through an internal 50-k ? resistor or can be pulled low through an internal 10-k ? resistor to prevent the pins from floating. the i/o pins may have the following states: tristated (high-z) weak pull-up (through internal 50 k ? ) pull down (through internal 10 k ? ) hold (i/o hold its value) when in low power modes all unused i/os should be pulled high by using the internal pull-up resistors. all unused outputs should be left floating. all i/os can be driven at full-strength, three-quarter strength, half-strength, or quarter-stren gth. these drive strengths are configured based on each interface. emi sd2 meets emi requirements outlined by fcc 15b (usa) and en55022 (europe) for consumer electronics. sd2 can tolerate reasonable emi, conducted by ag gressor, outlined by these specifications and continue to function as expected. system level esd sd2 has built-in esd protection on the d+, d?, gnd pins on the usb interface. the esd protection levels provided on these ports are: 2.2-kv human body model (hbm) based on jesd22-a114 specification 6-kv contact discharge and 8-kv air gap discharge based on iec61000-4-2 level 3a 8-kv contact discharge and 15-kv air gap discharge based on iec61000-4-2 level 4c. this protection ensures the device continues to function after esd events up to the levels stated. the s0/s1_ins have up to 2.2 kv hbm internal esd protection. pinout for bga figure 2. sd2 bga ball map (top view) 12 3 4 56 78 91011 a u3vssq u3 rx v ddq ssrx m ssrx p sstx p sstx m avdd vss dp dm nc b vio4 fslc[0] r_usb3 fslc[1] u3txvddq cvddq avss vss vss vdd nc c gpio[54] gpio[55] vdd gpio[57] reset# xtalin xtalout r_usb2 otg_id nc vio5 d gpio[ 50 ] gpio[ 51] gpio[ 52] gpio[ 53] gpio[ 56] clkin_32 clkin v ss i2c_gpio[ 58 ] i2c_gpio[ 59 ] o[ 6 0] e gpio[ 4 7] vss s1vddq gpio[49] gpio[48] fslc[2] nc nc vdd vbatt vbus f s0v ddq gpio[ 4 5] gpio[ 4 4] gpio[ 41] gpio[ 4 6] nc gpio[ 2 ] gpio[ 5] gpio[ 1] gpio[ 0] v dd g vss gpio[ 42] gpio[ 43] gpio[ 30] gpio[ 25] gpio[ 22] gpio[ 21] gpio[ 15] gpio[ 4] gpio[ 3] vss h vdd gpio[ 39] gpio[ 40] gpio[ 31] gpio[ 29] gpio[ 26] gpio[ 20] gpio[ 24] gpio[ 7] gpio[ 6] s2v ddq j gpio[ 38] gpio[ 36] gpio[ 37] gpio[ 34] gpio[ 28] gpio[ 16] gpio[ 19] gpio[ 14] gpio[ 9] gpio[ 8] vdd k gpio[ 3 5] gpio[ 33 ] vss vss gpio[27] gpio[23] gpio[18] gpio[17] gpio[13] gpio[12] gpio[10] l vss vss vss gpio[ 3 2] v dd vss v d d n c s 2 v d d q g p i o [ 11] vss
CYUSB202X document number: 001-87710 rev. *c page 9 of 27 pin description for bga table 7. pin list pin no. power domain i/o name description s2-port (gpio) f10 vi01 i/o gpio[0] gpio f9 vi01 i/o gpio[1] gpio f7 vi01 i/o gpio[2] gpio g10 vi01 i/o gpio[3] gpio g9 vi01 i/o gpio[4] gpio f8 vi01 i/o gpio[5] gpio h10 vi01 i/o gpio[6] gpio h9 vi01 i/o gpio[7] gpio j10 vi01 i/o gpio[8] gpio j9 vi01 i/o gpio[9] gpio k11 vi01 i/o gpio[10] gpio l10 vi01 i/o gpio[11] gpio k10 vi01 i/o gpio[12] gpio k9 vi01 i/o gpio[13] gpio j8 vi01 i/o gpio[14] gpio g8 vi01 i/o gpio[15] gpio j6 vi01 i/o gpio[16] gpio k8 vi01 i/o gpio[17] gpio k7 vi01 i/o gpio[18] gpio j7 vi01 i/o gpio[19] gpio h7 vi01 i/o gpio[20] gpio g7 vi01 i/o gpio[21] gpio g6 vi01 i/o gpio[22] gpio k6 vi01 i/o gpio[23] gpio h8 vi01 i/o gpio[24] gpio g5 vi01 i/o gpio[25] gpio h6 vi01 i/o gpio[26] gpio k5 vi01 i/o gpio[27] gpio j5 vi01 i/o gpio[28] gpio h5 vi01 i/o gpio[29] gpio g4 vi01 i/o gpio[30] pmode[0] h4 vi01 i/o gpio[31] pmode[1] l4 vi01 i/o gpio[32] pmode[2] l8 nc no connect c5 cvddq i reset# active low. hardware reset. 8b mmc configuration sd+gpio configuration gpio configuration k2 vi02 i/o gpio[33] s0_sd0 s0_sd0 gpio j4 vi02 i/o gpio[34] s0_sd1 s0_sd1 gpio k1 vi02 i/o gpio[35] s0_sd2 s0_sd2 gpio j2 vi02 i/o gpio[36] s0_sd3 s0_sd3 gpio j3 vi02 i/o gpio[37] s0_sd4 gpio gpio j1 vi02 i/o gpio[38] s0_sd5 gpio gpio
CYUSB202X document number: 001-87710 rev. *c page 10 of 27 h2 vi02 i/o gpio[39] s0_sd6 gpio gpio h3 vi02 i/o gpio[40] s0_sd7 gpio gpio f4 vi02 i/o gpio[41] s0_cmd s0_cmd gpio g2 vi02 i/o gpio[42] s0_clk s0_clk gpio g3 vi02 i/o gpio[43] s0_wp s0_wp gpio f3 vi02 i/o gpio[44] s0s1_ins s0s1_ins gpio f2 vi02 i/o gpio[45] mmc0_rst_out gpio gpio 8b mmc sd+uart sd+spi sd+gpio gpio gpio+ uart+i2s sd+i2s uart+spi+ i2s f5 vi03 i/o gpio[46] s1_sd0 s1_sd0 s1_s d0 s1_sd0 gpio gpio s1_sd0 uart_rts e1 vi03 i/o gpio[47] s1_sd1 s1_sd1 s1_s d1 s1_sd1 gpio gpio s1_sd1 uart_cts e5 vi03 i/o gpio[48] s1_sd2 s1_sd2 s1_s d2 s1_sd2 gpio gpio s1_sd2 uart_tx e4 vi03 i/o gpio[49] s1_sd3 s1_sd3 s1_s d3 s1_sd3 gpio gpio s1_sd3 uart_rx d1 vi03 i/o gpio[50] s1_cmd s1_cmd s1_cmd s1_cmd gpio i2s_clk s1_cmd i2s_clk d2 vi03 i/o gpio[51] s1_clk s1_clk s1_clk s1_clk gpio i2s_sd s1_clk i2s_sd d3 vi03 i/o gpio[52] s1_wp s1_wp s1_w p s1_wp gpio i2s_ws s1_wp i2s_ws d4 vio4 i/o gpio[53] s1_sd4 uart_rts spi_sck gpio gpio uart_rts gpio spi_sck c1 vio4 i/o gpio[54] s1_sd5 uart_cts spi_ssn gpio gpio uart_cts i2s_clk spi_ssn c2 vio4 i/o gpio[55] s1_sd6 uart_tx spi_miso gpio gpio uart_tx i2s_sd spi_miso d5 vio4 i/o gpio[56] s1_sd7 uart_rx spi_mosi gpio gpio uart_rx i2s_ws spi_mosi c4 vio4 i/o gpio[57] mmc1_rst_out gpio gpio gpio gpio i2s_mclk i2s_mclk i2s_mclk c9 nc no connect a3 nc usb 3.0 superspeed receive minus a4 nc usb 3.0 superspeed receive plus a6 nc usb 3.0 superspeed transmit minus a5 nc usb 3.0 superspeed transmit plus a9 vbatt/ vbus i/o d+ usb (hs/fs) data plus a10 vbatt/ vbus i/o d- usb (hs/fs) data minus a11 nc no connect b2 cvddq i fslc[0] fslc[0] c6 avdd i/o xtalin xtalin c7 avdd i/o xtalout xtalout b4 cvddq i fslc[1] fslc[1] e6 cvddq i fslc[2] fslc[2] d7 cvddq i clkin clkin d6 cvddq i clkin_32 clkin_32 d9 vio5 i/o i 2 c_gpio[58] scl (serial clock) for i 2 c bus interface d10 vio5 i/o i 2 c_gpio[59] sda (serial data) for i 2 c bus interface e7 nc no connect c10 nc no connect b11 nc no connect e8 nc no connect f6 nc no connect d11 vio5 o o[60] output only table 7. pin list (continued) pin no. power domain i/o name description
CYUSB202X document number: 001-87710 rev. *c page 11 of 27 e10 pwr vbatt b10 pwr vdd a1 pwr vss e11 pwr vbus d8 pwr vss h11 pwr vio1 e2 pwr vss l9 pwr vio1 g1 pwr vss f1 pwr vio2 g11 pwr vss e3 pwr vio3 l1 pwr vss b1 pwr vio4 l6 pwr vss b6 pwr cvddq b5 nc a2 nc c11 pwr vio5 l11 pwr vss a7 pwr avdd b7 pwr avss c3 pwr vdd b8 pwr vss e9 pwr vdd b9 pwr vss f11 pwr vdd h1 pwr vdd l7 pwr vdd j11 pwr vdd l5 pwr vdd k4 pwr vss l3 pwr vss k3 pwr vss l2 pwr vss a8 pwr vss precision resistors c8 vbus/ vbatt i/o r_usb2 precision resistor for usb 2.0 (connect a 6.04 k ? +/-1% resistor between this pin and gnd) b3 nc precision resistor for usb 3.0 (connect a 200 ? +/-1% resistor between this pin and gnd) table 7. pin list (continued) pin no. power domain i/o name description
CYUSB202X document number: 001-87710 rev. *c page 12 of 27 ac timing parameters storage port timing the s0-port and s1-port support the mmc specificatio n version 4.4 and sd specification version 2.0. ta b l e 7 lists the timing parameters for s0-por t and s1-port of sd2. table 8. s-port timing parameters [2] parameter description min max units mmc-20 tsdis cmd host input setup time for cmd 4.8 ? ns tsdis dat host input setup time for dat 4.8 ? ns tsdih cmd host input hold time for cmd 4.4 ? ns tsdih dat host input hold time for dat 4.4 ? ns tsdos cmd host output setup time for cmd 5 ? ns tsdos dat host output setup time for dat 5 ? ns tsdoh cmd host output hold time for cmd 5 ? ns tsdoh dat host output hold time for dat 5 ? ns tsclkr clock rise time ? 2 ns tsclkf clock fall time ? 2 ns tsdck clock cycle time 50 ? ns sdfreq clock frequency 20 mhz tsdclkod clock duty cycle 40 60 % mmc-26 tsdis cmd host input setup time for cmd 10 ? ns tsdis dat host input setup time for dat 10 ? ns tsdih cmd host input hold time for cmd 9 ? ns tsdih dat host input hold time for dat 9 ? ns tsdos cmd host output setup time for cmd 3 ? ns tsdos dat host output setup time for dat 3 ? ns tsdoh cmd host output hold time for cmd 3 ? ns tsdoh dat host output hold time for dat 3 ? ns tsclkr clock rise time ? 2 ns tsclkf clock fall time ? 2 ns tsdck clock cycle time 38.5 ? ns sdfreq clock frequency 26 mhz tsdclkod clock duty cycle 40 60 % mc-hs tsdis cmd host input setup time for cmd 4 ? ns tsdis dat host input setup time for dat 4 ? ns tsdih cmd host input hold time for cmd 3 ? ns tsdih dat host input hold time for dat 3 ? ns tsdos cmd host output setup time for cmd 3 ? ns tsdos dat host output setup time for dat 3 ? ns tsdoh cmd host output hold time for cmd 3 ? ns tsdoh dat host output hold time for dat 3 ? ns
CYUSB202X document number: 001-87710 rev. *c page 13 of 27 tsclkr clock rise time ? 2 ns tsclkf clock fall time ? 2 ns tsdck clock cycle time 19.2 ? ns sdfreq clock frequency ? 52 mhz tsdclkod clock duty cycle 40 60 % mmc-ddr52 tsdis cmd host input setup time for cmd 4 ? ns tsdis dat host input setup time for dat 0.56 ? ns tsdih cmd host input hold time for cmd 3 ? ns tsdih dat host input hold time for dat 2.58 ? ns tsdos cmd host output setup time for cmd 3 ? ns tsdos dat host output setup time for dat 2.5 ? ns tsdoh cmd host output hold time for cmd 3 ? ns tsdoh dat host output hold time for dat 2.5 ? ns tsclkr clock rise time ? 2 ns tsclkf clock fall time ? 2 ns tsdck clock cycle time 19.2 ? ns sdfreq clock frequency 52 mhz tsdclkod clock duty cycle 45 55 % sd-default speed (sdr12) tsdis cmd host input setup time for cmd 24 ? ns tsdis dat host input setup time for dat 24 ? ns tsdih cmd host input hold time for cmd 2.5 ? ns tsdih dat host input hold time for dat 2.5 ? ns tsdos cmd host output setup time for cmd 5 ? ns tsdos dat host output setup time for dat 5 ? ns tsdoh cmd host output hold time for cmd 5 ? ns tsdoh dat host output hold time for dat 5 ? ns tsclkr clock rise time ? 2 ns tsclkf clock fall time ? 2 ns tsdck clock cycle time 40 ? ns sdfreq clock frequency 25 mhz tsdclkod clock duty cycle 40 60 % sd-high-speed(sdr25) tsdis cmd host input setup time for cmd 4 ? ns tsdis dat host input setup time for dat 4 ? ns tsdih cmd host input hold time for cmd 2.5 ? ns tsdih dat host input hold time for dat 2.5 ? ns tsdos cmd host output setup time for cmd 6 ? ns tsdos dat host output setup time for dat 6 ? ns tsdoh cmd host output hold time for cmd 2 ? ns tsdoh dat host output hold time for dat 2 ? ns table 8. s-port timing parameters [2] (continued) parameter description min max units
CYUSB202X document number: 001-87710 rev. *c page 14 of 27 tsclkr clock rise time ? 2 ns tsclkf clock fall time ? 2 ns tsdck clock cycle time 20 ? ns sdfreq clock frequency ? 50 mhz tsdclkod clock duty cycle 40 60 % sd-sdr50 tsdis cmd host input setup time for cmd 1.5 ? ns tsdis dat host input setup time for dat 1.5 ? ns tsdih cmd host input hold time for cmd 2.5 ? ns tsdih dat host input hold time for dat 2.5 ? ns tsdos cmd host output setup time for cmd 3 ? ns tsdos dat host output setup time for dat 3 ? ns tsdoh cmd host output hold time for cmd 0.8 ? ns tsdoh dat host output hold time for dat 0.8 ? ns tsclkr clock rise time ? 2 ns tsclkf clock fall time ? 2 ns tsdck clock cycle time 10 ? ns sdfreq clock frequency 100 mhz tsdclkod clock duty cycle 40 60 % sd-ddr50 tsdis cmd host input setup time for cmd 4 ? ns tsdis dat host input setup time for dat 0.92 ? ns tsdih cmd host input hold time for cmd 2.5 ? ns tsdih dat host input hold time for dat 2.5 ? ns tsdos cmd host output setup time for cmd 6 ? ns tsdos dat host output setup time for dat 3 ? ns tsdoh cmd host output hold time for cmd 0.8 ? ns tsdoh dat host output hold time for dat 0.8 ? ns tsclkr clock rise time ? 2 ns tsclkf clock fall time ? 2 ns tsdck clock cycle time 20 ? ns sdfreq clock frequency 50 mhz tsdclkod clock duty cycle 45 55 % table 8. s-port timing parameters [2] (continued) parameter description min max units note 2. all parameters guaranteed by design and validated through characterization.
CYUSB202X document number: 001-87710 rev. *c page 15 of 27 i 2 c interface timing i 2 c timing figure 3. i 2 c timing definition table 9. i 2 c timing parameters [3] parameter description min max units i 2 c standard mode parameters fscl scl clock frequency 0 100 khz thd:sta hold time start condition 4 ? s tlow low period of the scl 4.7 ? s thigh high period of the scl 4 ? s tsu:sta setup time for a repeated start condition 4.7 ? s thd:dat data hold time 0 ? s tsu:dat data setup time 250 ? ns tr rise time of both sda and scl signals ? 1000 ns tf fall time of both sda and scl signals ? 300 ns tsu:sto setup time for stop condition 4 ? s tbuf bus free time between a stop and start condition 4.7 ? s tvd:dat data valid time ? 3.45 s tvd:ack data valid ack ? 3.45 s tsp pulse width of spikes that must be suppressed by input filter n/a n/a note 3. all parameters guaranteed by design and validated through characterization.
CYUSB202X document number: 001-87710 rev. *c page 16 of 27 i 2 c fast mode parameters fscl scl clock frequency 0 400 khz thd:sta hold time start condition 0.6 ? s tlow low period of the scl 1.3 ? s thigh high period of the scl 0.6 ? s tsu:sta setup time for a repeated start condition 0.6 ? s thd:dat data hold time 0 ? s tsu:dat data setup time 100 ? ns tr rise time of both sda and scl signals ? 300 ns tf fall time of both sda and scl signals ? 300 ns tsu:sto setup time for stop condition 0.6 ? s tbuf bus-free time between a stop and start condition 1.3 ? s tvd:dat data valid time ? 0.9 s tvd:ack data valid ack ? 0.9 s tsp pulse width of spikes that must be suppressed by input filter 0 50 ns i 2 c fast mode plus parameters (not supported at i2c_vddq=1.2v) fscl scl clock frequency 0 1000 khz thd:sta hold time start condition 0.26 ? s tlow low period of the scl 0.5 ? s thigh high period of the scl 0.26 ? s tsu:sta setup time for a repeated start condition 0.26 ? s thd:dat data hold time 0 ? s tsu:dat data setup time 50 ? s tr rise time of both sda and scl signals ? 120 ns tf fall time of both sda and scl signals ? 120 ns tsu:sto setup time for stop condition 0.26 ? s tbuf bus free time between a stop and start condition 0.5 ? s tvd:dat data valid time ? 0.45 s tvd:ack data valid ack ? 0.55 s tsp pulse width of spikes that must be suppressed by input filter 0 50 ns table 9. i 2 c timing parameters [3] (continued) parameter description min max units
CYUSB202X document number: 001-87710 rev. *c page 17 of 27 i 2 s timing diagram figure 4. i 2 s transmit cycle t t t tr t tf t tl t thd t td t th sck sa, ws (output) table 10. i 2 s timing parameters [4] parameter description min max units tt i 2 s transmitter clock cycle ttr ? ns ttl i 2 s transmitter cycle low period 0.35 ttr ? ns tth i 2 s transmitter cycle high period 0.35 ttr ? ns ttr i 2 s transmitter rise time ? 0.15 ttr ns ttf i 2 s transmitter fall time ? 0.15 ttr ns tthd i 2 s transmitter data hold time 0 ? ns ttd i 2 s transmitter delay time ? 0.8tt ns note tt is selectable through clock gears. max ttr is designed for 96-khz codec at 32 bits to be 326 ns (3.072 mhz). note 4. all parameters guaranteed by design and validated through characterization.
CYUSB202X document number: 001-87710 rev. *c page 18 of 27 spi timing specification figure 5. spi timing lsb lsb msb msb lsb lsb msb msb t lead t sck t sdd t hoi t wsck t wsck t lag t d v t rf t ssnh t dis t sdi t lead t sck t wsck t wsck t lag t rf t ssnh t sdi t dis t dv t hoi ssn (output) sck (cpol=0, output) sck (cpol=1, output) miso (input) mosi (output) ssn (output) sck (cpol=0, output) sck (cpol=1, output) miso (input) mosi (output) spi master timing for cpha = 0 spi master timing for cpha = 1 t di t di
CYUSB202X document number: 001-87710 rev. *c page 19 of 27 table 11. spi timing parameters [5] parameter description min max units fop operating frequency 0 33 mhz tsck cycle time 30 ? ns twsck clock high/low time 13.5 ? ns tlead ssn-sck lead time 1/2 tsck [6] - 5 1.5 tsck [6] + 5 ns tlag enable lag time 0.5 1.5 tsck [6] +5 ns trf rise/fall time ? 8 ns tsdd output ssn to valid data delay time ? 5 ns tdv output data valid time ? 5 ns tdi output data invalid 0 ? ns tssnh minimum ssn high time 10 ? ns tsdi data setup time input 8 ? ns thoi data hold time input 0 ? ns tdis disable data output on ssn high 0 ? ns notes 5. all parameters guaranteed by design and validated through characterization. 6. depends on lag and lead setting in the spi_config register.
CYUSB202X document number: 001-87710 rev. *c page 20 of 27 absolute maximum ratings exceeding maximum ratings may shorten the useful life of the device. storage temperature .................................... ?65 c to +150 c ambient temperature with power supplied (industri al) ............................ ?40 c to +85 c supply voltage to ground potential v dd , a vddq ..................................................................... 1.25 v s2 vddq ,s1 vddq , s0 vddq , v io4 , v io5 .............................. 3.6 v u3tx vddq , u3rx vddq .................................................. 1.25 v dc input voltage to any input pin .............................. vcc + 0.3 dc voltage applied to outputs in high z state ............................................. vcc + 0.3 (vcc is the corresponding i/o voltage) static discharge voltage esd protection levels: 2.2-kv human body model (hbm) based on jesd22-a114 additional esd protection levels on d+, d?, vbus, gnd pins u-port and gpio pins lpp-port 6-kv contact discharge, 8-kv air gap discharge based on iec61000-4-2 level 3a, 8-kv contact discharge, and 15-kv air gap discharge based on iec61000-4-2 level 4c latch-up current ........................................................ > 200 ma maximum output short circuit current for all i/o configurations. (vout = 0 v) ............. ........... ?100 ma operating conditions ta (ambient temperature under bias) industrial ........................................................ ?40 c to +85 c v dd , a vddq , u3tx vddq , u3rx vddq supply voltage .................................................. 1.15 v to 1.25 v v batt supply voltage .............................................. 3.2 v to 6 v s2 vddq , s1 vddq , s0 vddq , v io4 , c vddq supply voltage ...................................................... 1.7 v to 3.6 v v io5 supply voltage ............................................ 1.15 v to 3.6 v dc specifications table 12. dc specifications parameter description min max units notes v dd core voltage supply 1.15 1.25 v 1.2-v typical a vdd analog voltage supply 1.15 1.25 v 1.2-v typical v io2 sd/ mmc/ cf i/o power supply domain 1.7 3.6 v 1.8-, 2.5-, and 3.3-v typical v io3 sd/mmc i/o power supply domain 1.7 3.6 v 1.8-, 2.5-, and 3.3-v typical v io1 gpio/ cf i/o power supply domain 1.7 3.6 v 1.8-, 2.5-, and 3.3-v typical v io4 gpio/ i/o power supply domain 1.7 3.6 v 1.8-, 2.5-, and 3.3-v typical v batt usb voltage supply 3.2 6 v 3.7-v typical v bus usb voltage supply 4.0 6 v 5-v typical c vddq clock voltage supply 1.7 3.6 v 1.8-, 3.3-v typical v io5 i 2 c voltage supply 1.2 3.3 v 1.2-,1.8-, 2.5-, and 3.3-v typical v ih1 input high voltage 1 0.625 vcc vcc + 0.3 v for 2.0 v ? v cc ? 3.6 v (except usb port).vcc is the corre- sponding i/o voltage supply. v ih2 input high voltage 2 vcc - 0.4 vcc + 0.3 v for 1.7 v ? v cc ?? 2.0 v (except usb port). vcc is the corresponding i/o voltage supply. v il input low voltage ?0.3 0.25 vcc v vcc is the corresponding i/o voltage supply. v oh output high voltage 0.9 vcc ? v i oh (max) = ?100 a tested at quarter drive strength. vcc is the corresponding i/o voltage supply. v ol output low voltage ? 0.1 vcc v i ol (min) = +100 a tested at quarter drive strength. vcc is the corresponding i/o voltage supply.
CYUSB202X document number: 001-87710 rev. *c page 21 of 27 i ix input leakage current for all pins except sstxp/ssxm/ssrxp/ssrxm ?1 1 a all i/o signals held at v ddq (for i/os that have a pull-up/down resistor connected, the leakage current increases by v ddq /r pu or v ddq /r pd i oz output high-z leakage current for all pins except sstxp/ssxm/ssrxp/ssrxm ?1 1 a all i/o signals held at vddq i cc core core and analog voltage operating current ? 150 ma total current through avdd, vdd i cc usb usb voltage supply operating current ? 20 ma i sb1 total suspend current during suspend mode with usb 3.0 phy enabled (l1 mode) ? ? ma core current: 1.5 ma i/o current: 20 ua usb current: 2 ma for typical pvt (typical silicon, all power supplies at their respective nominal levels at 25 ? c.) i sb2 total suspend current during suspend mode with usb 3.0 phydisabled (l2 mode) ? ? ma core current: 250 ua i/o current: 20 ua usb current: 1.2 ma for typical pvt (typical silicon, all power supplies at their respective nominal levels at 25 ? c.) i sb3 total standby current during standby mode (l3 mode) ? ? a core current: 60 ua i/o current: 20 ua usb current: 40 ua for typical pvt (typical silicon, all power supplies at their respective nominal levels at 25 ? c.) i sb4 total standby current during core power down mode (l4 mode) ? ? a core current: 0 ua i/o current: 20 ua usb current: 40 ua for typical pvt (typical silicon, all power supplies at their respective nominal levels at 25 ? c.) v ramp voltage ramp rate on core and i/o supplies 0.2 50 v/ms voltage ramp must be monotonic v n noise level permitted on vdd and i/o supplies ? 100 mv max p-p noise level permitted on all supplies except a vdd v n_avdd noise level permitted on avdd supply ? 20 mv max p-p noise level permitted on a vdd table 12. dc specifications (continued) parameter description min max units notes
CYUSB202X document number: 001-87710 rev. *c page 22 of 27 reset sequence the hard reset sequence requirements for sd2 are specified in the following table. figure 6. reset sequence table 13. reset and standby timing parameters parameter definition conditions min (ms) max (ms) trpw minimum reset# pulse width clock input 1 ? crystal input 1 ? trh minimum high on reset# 5 ? trr reset recovery time (after which boot loader begins firmware download) clock input 1 ? crystal input 5 tsby time to enter standby/suspend (from the time main_clock_en/ main_power_en bit is set) ?1 twu time to wakeup from standby clock input 1 ? crystal input 5 ? twh minimum time before standby/suspend source may be reasserted 5? vdd (core) xvddq xtalin/ clkin reset # mandatory reset pulse hard reset trpw trh standby/ suspend source standby/suspend source is asserted (main_power_en/ main_clk_en bit is set) standby/suspend source is deasserted tsby twu xtalin/ clkin must be stable before exiting standby/suspend trr twh
CYUSB202X document number: 001-87710 rev. *c page 23 of 27 package diagram figure 7. 121-ball fbga (10 10 1.20 mm) package outline, 001-54471 n is the number of populated solder ball positions for matrix when there is an even number of solder balls in the outer row, when there is an odd number of solder balls in the outer row, define the position of the center solder ball in the outer row. "sd" and "se" are measured with respect to datums a and b and symbol "me" is the ball matrix size in the "e" direction. symbol "md" is the ball matrix size in the "d" direction. "e" represents the solder ball grid pitch. dimension "b" is measured at the maximum ball diameter in a solder ball position designation per jep95, section 3, spp-020. "+" indicates the theoretical center of depopulated solder a1 corner to be identified by chamfer, laser or ink mark 8. 7. 6. notes: 5. 4. 3. 2. 1. all dimensions are in millimeters. sd b ee ed me n 0.25 0.00 0.80 bsc 0.80 bsc 0.30 121 11 0.35 dimensions d1 md e1 e d a a1 symbol 0.15 min. - 8.00 bsc 8.00 bsc 11 10.00 bsc 10.00 bsc nom. - 1.20 - max. se 0.00 - metalized mark, indentation or other means. "sd" = ed/2 and "se" = ee/2. plane parallel to datum c. "sd" or "se" = 0. size md x me. balls. 7654321 11 10 9 8 l k j h g f e d c b a 121x?b 5 ?0.15 c m c ?0.08 m ab c a1 0.08 c 0.20 c detail a top view bottom view side view a detail a a1 corner 7 a1 corner a e d 0.10 2x c b 0.10 2x c d1 e1 (datum a) (datum b) sd 6 se 6 ed ee 001-54471 *e
CYUSB202X document number: 001-87710 rev. *c page 24 of 27 ordering information ordering code definitions table 14. ordering information ordering code sd/emmc sdio ports sram (kb) package type cyusb2024-bzxi 2 512 121-ball bga cyusb2025-bzxi 2 512 121-ball bga x = blank or t blank = tube; t = tape and reel temperature range: i = industrial pb-free package type: bz = 121-ball bga marketing part number base part number for usb 2.0 marketing code: usb = usb controller company id: cy = cypress cy bz x usb 2 xxx x - i
CYUSB202X document number: 001-87710 rev. *c page 25 of 27 acronyms document conventions units of measure acronym description aca accessory charger adaptor bga ball grid array mmc multimedia card pll phase locked loop sd secure digital sdio secure digital input / output slc single-level cell usb universal serial bus symbol unit of measure c degree celsius a microamperes s microseconds ma milliamperes mbps megabytes per second mhz mega hertz ms milliseconds ns nanoseconds ? ohms pf pico farad vvolts
CYUSB202X document number: 001-87710 rev. *c page 26 of 27 document history page document title: CYUSB202X, sd2? usb and mass storage peripheral controller document number: 001-87710 revision ecn orig. of change submission date description of change ** 4016299 gsz 05/31/2013 new data sheet. *a 4114923 gsz 09/05/2013 changed status from ?company confidential? to ?final?. updated in new template. *b 5329287 rajv 06/29/2016 updated the package diagram to current revision. updated the cypress logo and copyright information. *c 5708850 aesatmp7 04/24/2017 updated cypress logo and copyright.
document number: 001-87710 rev. *c revised april 24, 2017 page 27 of 27 CYUSB202X ? cypress semiconductor corporation, 2013-2017. this document is the property of cypress semiconductor corporation and its subs idiaries, including spansion llc ("cypress"). this document, including any software or firmware included or referenced in this document ("software"), is owned by cypress under the intellec tual property laws and treaties of the united states and other countries worldwide. cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragr aph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. if the software is not accompanied by a license agreement and you do not otherwise have a writte n agreement with cypress governing the use of the software, then cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the software (a) for software provided in source code form, to modify and reproduce the software solely for use with cypress hard ware products, only internally within your organization, and (b) to distribute the software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on cypress hardware product units, and (2) u nder those claims of cypress's patents that are infringed by the software (as provided by cypress, unmodified) to make, use, distribute, and import the software solely for use with cypress hardware product s. any other use, reproduction, modi fication, translation, or compilation of the software is prohibited. to the extent permitted by applicable law, cypress makes no warranty of any kind, express or implied, with regard to this docum ent or any software or accompanying hardware, including, but not limited to, the im plied warranties of merchantability and fitness for a particular purpose. to the extent permitted by applicable law, cypress reserves the right to make changes to this document without further notice. cypress does n ot assume any liability arising out of the application or use of any product or circuit described in this document. any information provided in this document, including any sample design informat ion or programming code, is provided only for reference purposes. it is the responsibility of the user of this document to properly desig n, program, and test the functionality and safety of any appli cation made of this information and any resulting product. cypress products are not designed, intended, or authorized fo r use as critical components in systems de signed or intended for the operation of w eapons, weapons systems, nuclear inst allations, life-support devices or systems, other medical devices or systems (inc luding resuscitation equipment and surgical implants), pollution control or hazar dous substances management, or other uses where the failure of the device or system could cause personal injury , death, or property damage ("unintended uses"). a critical component is any compon ent of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affe ct its safety or effectiveness. cypress is not liable, in whol e or in part, and you shall and hereby do release cypress from any claim, damage, or other liability arising from or related to all unintended uses of cypress products. you shall indemnify and hold cyp ress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal inju ry or death, arising from or related to any unintended uses of cypress products. cypress, the cypress logo, spansion, the spansion logo, and combinations thereof, wiced, psoc, capsense, ez-usb, f-ram, and tra veo are trademarks or registered trademarks of cypress in the united states and other countries. for a more complete list of cypress trademarks, visit cypress.com. other names and brand s may be claimed as property of their respective owners. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution cent ers, manufacturer?s representativ es, and distributors. to find t he office closest to you, visit us at cypress locations . products arm ? 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